1. Field of the Invention
The present invention relates to a method of forming the capacitor of a semiconductor memory device. More particularly, the present invention relates to a method of forming the crown-shaped capacitor of a dynamic random access memory (DRAM).
2. Description of the Related Art
In integrated circuits with deep-submicron line width, the dimension of each device is greatly reduced. Consequently, space left for forming the capacitor of a DRAM unit shrinks. However, due to the rapid increase in size of software programs, there is an exponential increase in memory requirement. Hence, small-size high-capacity memory cells are in great demand. To obtain a miniature high-capacity memory cell, fundamental changes to the conventional method of fabricating memory cells have to be made.
Stack type capacitor has been used in semiconductor cells for quite some time. In the fabrication of deep submicron devices, stack type capacitors continue to be developed. Stack type capacitors are formed into a variety of shapes including crown shape, fin shape, cylindrical shape or spread-out shape. Though stack type capacitor is capable of cramming a large number of memory units into a single cell to create high-density DRAM, forming a memory cell capable of storing 256 megabits (Mb) or higher is still difficult.
FIGS. 1A through 1E are schematic cross-sectional views showing the progression of steps for producing a conventional double-sided crown-shaped capacitor.
As shown in FIG. 1A, a substrate 100 having a device therein is provided. A silicon oxide layer 102 and a silicon nitride layer 104 are sequentially formed over the substrate 100 and the device. The silicon oxide layer 102 functions as an inter-layer dielectric (ILD) while the silicon nitride layer 104 functions as an etching stop layer for forming the double-sided crown-shaped structure. Photolithographic and etching techniques are next applied to form a contact opening 106 through the silicon oxide layer 102 and the silicon nitride layer 104. A doped polysilicon plug 107 is formed inside the contact opening 106.
As shown in FIG. 1B, an insulation layer 108 is formed over the silicon nitride layer 104 and the polysilicon plug 107. Photolithographic and etching processes are then carried out to form an opening 110 in the insulation layer 108 so that the polysilicon plug 107 and a portion of the silicon nitride layer 104 are exposed.
As shown in FIG. 1C, a conformal amorphous silicon layer 112 is formed over the insulation layer 108 and the exposed interior surfaces of the opening 110.
As shown in FIG. 1D, the amorphous silicon layer 112 above the insulation layer 108 is removed using the insulation layer 108 as a polishing stop layer. Ultimately, only an amorphous silicon layer 112a remains inside the opening 110
As shown in FIG. 1E, the insulation layer 108 above the silicon nitride layer 104 is removed using the silicon nitride layer 104 as an etching stop layer. Hence, a double-sided crown-shaped capacitor structure is formed. In a subsequent step, steps may be taken to grow hemispherical polysilicon grains over the exposed amorphous silicon layer 112a. A capacitor dielectric layer and an upper electrode are sequentially formed over the amorphous silicon layer 112a to complete the fabrication of the crown-shaped capacitor.
Although the crown-shaped capacitors formed by the aforementioned method occupy very little space, capacitance of each capacitor is too small to form the memory unit of a 256M or 1 G DRAM.